1. Field of the Invention
The present invention relates to a semiconductor memory device capable of electrically rewriting, particularly to a technique for forming a memory cell with a fine structure.
2. Related Background Art
FIG. 1 is a view showing a sectional structure of a cell of a conventional M(O)NOS type EEPROM. A memory cell of FIG. 1 has a memory cell transistor 53 formed on the upper surface of a p-type well area 52 on an n-type silicon substrate 51, and first and second selecting transistors 54 and 55. A gate insulating film 56 of the memory cell transistor 53 has a laminated structure constituted of a silicon oxide film 57, a silicon nitride film 58, a tunnel oxide film 59, and the silicon nitride film 58 is utilized as an electric charge accumulating layer of electrons injected through a direct tunnel from the substrate 52.
When data is written to the EEPROM having the structure as shown in FIG. 1, data are first erased from all the memory cells in a predetermined cell block. Specifically, a positive high voltage is applied to the p-type well area 52, and electrons are discharged to the p-type well area 52 from the silicon nitride film 58 through the direct tunnel, whereby all the memory cells are in normally on states.
Next, data is written to a desired memory cell. Specifically, by designating the first selecting transistor 54, a control gate of the memory cell transistor 53, and a bit line (not shown), an arbitrary memory cell is selected. The writing to the memory cell transistor 53 is performed by setting the bit line to a ground level, and applying a high voltage to the first selecting transistor 54 and the control gate 53, while the second selecting transistor 55 is turned off, whereby electrons are injected to the silicon nitride film 58 from the substrate 52 through the direct tunnel.
The control gate 53 of FIG. 1 is shared by a plurality of memory cells, and in order to avoid the writing of the data to a non-selected memory cell, the bit line of the non-selected memory cell is set to an intermediate voltage. Moreover, the second selecting transistor 55 is set to an off state so that no through current may flow from the bit line to a source side.
The EEPROM of FIG. 1 has the following problems (1) and (2):
(1) Since each memory cell requires two selecting transistors 54 and 55, a cell size is unavoidably enlarged, and it is difficult to enlarge a memory capacity. PA1 (2) Since there is provided a structure in which the electric charge written to the silicon nitride film 58 passes toward the substrate by direct tunneling and a so-called electric charge falling easily occurs, a charge holding property is inferior. PA1 (3) During writing, a large amount of the program current having a mA level flows in a single unit of memory cell 1. PA1 (4) For patterns to form diffusion layer wiring, selecting transistors, and the like, since voltage drop is relatively large, writing properties are deteriorated, and a dispersion of threshold voltage is also enlarged. Therefore, it is difficult to simultaneously write to multiple bias. PA1 (5) Since there is provided a two-layer gate structure, the structure is complicated, and manufacturing processes also become complicated. PA1 a first diffusion layer area and a first channel area formed in contact with each other in a direction substantially parallel to the upper surface of a semiconductor substrate; PA1 a second channel area formed in contact with said first channel area in the direction substantially parallel to the upper surface of said semiconductor substrate; PA1 a second diffusion layer area formed in contact with said second channel area in the direction substantially parallel to the upper surface of said semiconductor substrate; PA1 a charge accumulating layer of a laminated structure formed on said first channel area; PA1 an insulating layer formed on said charge accumulating layer; and PA1 a gate electrode formed on the upper surface of said charge accumulating layer and said insulating layer, PA1 a threshold voltage of said first channel area under said gate electrode being set to be higher than a threshold voltage of said second channel area under said gate electrode. PA1 a virtual ground type memory cell array in which a memory cell having a control gate and a floating gate is arranged in a row direction and a column direction in a matrix manner, control gates of the memory cells of the same row are connected in common to constitute a row line, sources of the memory cells of the same column are connected in common to constitute a source line, and drains of the memory cells of the same column are connected in common to constitute a drain line; PA1 first to sixth selection gate lines; PA1 a plurality of first source line selecting transistors having gate terminals connected in common to said first selection gate line to select the corresponding source lines, respectively; PA1 a plurality of second source line selecting transistors having gate terminals connected in common to said second selection gate line to select the corresponding source lines, respectively; PA1 a plurality of third source line selecting transistors having gate terminals connected in common to said third selection gate line to select the corresponding source lines, respectively; PA1 a plurality of first drain line selecting transistors having gate terminals connected in common to said fourth selection gate line to select the corresponding drain lines, respectively; PA1 a plurality of second drain line selecting transistors having gate terminals connected in common to said fifth selection gate line to select the corresponding drain lines, respectively; and PA1 a plurality of third drain line selecting transistors having gate terminals connected in common to said sixth selection gate line to select the corresponding drain lines, respectively, wherein PA1 a memory cell transistor formed on a semiconductor substrate and having a charge accumulating layer to which electrons from the semiconductor substrate can be injected; PA1 a selecting transistor formed adjacent to said memory cell transistor and having a selection gate; and PA1 a source area and a drain area formed in the semiconductor substrate on opposite sides of said memory cell transistor and said selecting transistor, wherein
As one technique for solving the above problems (1) and (2), a virtual ground array type EPROM or EEPROM is proposed.
FIG. 2 is a schematic sectional view of the virtual ground array type EEPROM, and FIG. 3 is a circuit diagram showing an inner configuration of the virtual ground array type EPROM.
In the virtual ground array type EEPROM or EPROM, as shown in FIG. 3, there is provided a memory cell array 2 in which a plurality of memory cells are arranged in a matrix manner. Control gates in the memory cells of the same row in the memory cell array 2 are connected in common to constitute a word line. Moreover, sources and drains of memory cells 1 adjacent to each other in a column direction are interconnected, and sources and drains of the same column are connected in common to constitute a column line.
As shown in FIG. 2, each memory cell 1 is provided with a floating gate 61 and a control gate 62, and in a lower semiconductor substrate 63, n.sup.+ diffusion layer 64 and n.sup.- diffusion layer 65 are formed for use as a source area and a drain area. Specifically, the n.sup.+ diffusion layer 64 forms the source area, and the n.sup.- diffusion layer 65 forms the drain area. Moreover, the floating gate 61 is formed to overlap the n.sup.+ diffusion layer 64 and the n.sup.- diffusion layer 65.
When data is written to the EEPROM of FIG. 2, the source diffusion layer is set to a ground level, and a high voltage is applied to the word line and the drain diffusion layer. Thereby, hot electrons are injected to the floating gate 61 from the drain side.
For the non-selected cell adjacent to the source side of the selected cell, data writing is avoided by setting the drain diffusion layer to the ground level. Moreover, for the non-selected cell adjacent to the drain side of the selected cell, the data writing is avoided by setting the drain diffusion layer and the source diffusion layer to the same potential, whereby, program current is reduced.
The EEPROM of FIG. 2 has the following problems (3) and (4):
As described above, because of the problems (3) to (5), even when EEPROM circuit structure is of the virtual ground array type, good electric properties cannot be obtained. As a result, it becomes difficult to enlarge the memory capacity.
When data is erased from EPROM of FIG. 3, ultraviolet rays are radiated from above the semiconductor substrate, and electrons are discharged from the floating gate. Moreover, data is read from EPROM of FIG. 3 in the following procedure. For example, when data is read from a memory cell 1a of FIG. 3, all selection gates SG1 to SG4 are set to power supply voltage Vdd, a gate line Gn connected to the memory cell 1a is set to the power supply voltage Vdd, the other gate lines are set to ground voltage Vss, all source contacts on the left side from source contact SC1 are set to the ground voltage Vss, all source contacts on the right side from source contact SC2 are set to the power supply voltage Vdd, all drain contacts on the left side from drain contact DC1 are set to the ground voltage Vss, and all drain contacts on the right side from drain contact DC2 are set to the power supply voltage Vdd, so that "0" or "1" is distinguished in accordance with the amount of electric current flowing into the drain contact DC2.
Similarly, when data is read from memory cells 1b, 1c and 1d of FIG. 3, voltages as shown in FIG. 4 are applied to the selection gates SG1 to SG4, gate lines G1 to Gm, source contacts SC1 to SC3, and drain contacts DC1 to DC3, respectively.
On the other hand, data is written to EPROM of FIG. 3 in the following procedure. For example, when data is written to the memory cell 1a of FIG. 3, all the selection gates SG1 to SG4 are set to power supply voltage Vdd, the gate line Gn connected to the memory cell 1a is set to a voltage Vpd which is higher than the power supply voltage Vdd, the other gate lines are set to the ground voltage Vss, all the source contacts on the left side of the source contact SC1 are set to the ground voltage Vss, all the source contacts on the right side of the source contact SC2 are set to the voltage Vpd, all the drain contacts on the left side of the drain contact DC1 are set to the ground voltage Vss, and all the drain contacts on the right side of the drain contact DC2 are set to the voltage Vpd. In this state, electrons are injected to the floating gate from a channel section of the memory cell 1a. By the above-described operation, the threshold voltage of the memory cell 1 in which the electrons are injected to the floating gate can be set to be higher than the power supply voltage Vdd.
Similarly, a method of setting voltages when data is written to the memory cells 1b, 1c, and 1d of FIG. 3 is as shown in FIG. 5.
When data is written to EPROM of FIG. 3, there arises a problem that some of the source and drain lines are in floating states, which causes a possibility that data is written to the non-selected cells by mistake.
For example, FIG. 6 is a diagram showing voltages of the source and drain lines when data is written to the memory cell 1b. As shown in the drawing, the voltage Vpd is applied to drain line D21 of the memory cell 1b, and the ground voltage Vss is applied to source line S21, so that data is written to the memory cell 1b. In this case, drain line D22 adjacent to the right side of the source line S21 is in a floating (F) state. Therefore, data is probably written by mistake to the memory cell 1d until the source line S22 reaches the ground voltage Vss. Similarly, when data is written to the memory cell 1d, there is a possibility that data is written by mistake to the adjacent memory cell 1c.
Incidentally, there is proposed a so-called source side injection type EEPROM in which electrons are injected into the floating gate from the source side. FIG. 7 is a sectional view showing a basic structure of the source side injection type EEPROM.
The EEPROM of FIG. 7 has a structure in which a memory cell transistor 63 and a selecting transistor 64 are arranged adjacent to each other between a source area 61 and a drain area 62. The memory cell transistor 63 has a control gate 65 and a floating gate 66, and the selecting transistor 64 has a selection gate 67. The floating gate 66 is usually formed of poly-silicon.
During data (electron) writing, a high voltage is applied to the control gate 65, a predetermined voltage is applied between drain and source, and a voltage which is slightly higher than the threshold voltage of the selecting transistor 64 is applied to the selection gate 67. Thereby, electrons are injected to the floating gate 66 from the source side of the floating gate 66.
The operation principle is as follows:
In a writing bias state, the floating gate 66 becomes an intermediate voltage by coupling of the floating gate 66 and the control gate 65. A channel under the floating gate 66 requires a negative charge matching the potential of the floating gate 66, but a channel current is suppressed to be low by the selecting transistor 64. Therefore, a negative charge amount by a channel electron is insufficient. To compensate for this insufficiency, a deep depletion layer S is formed under the floating gate 66 so as to ionize a donor of substrate impurities.
Specifically, an energy level of Si substrate surface is deeply lowered. Then, an energy level of an oxide film on Si substrate under the floating gate 66 is also deeply lowered. Thereby, an energy barrier of Si oxide film is maintained.
In this state, an electron, which has penetrated into a channel area under the floating gate 66 through a channel of the selection gate 67 from the source area 61 without losing its energy, reaches an energy level higher than an energy level of a conductive band of the oxide film on the upper surface, and further advances. Subsequently, the electron flows along an electric field between the floating gate 66 and the substrate, flows beyond the energy barrier of the oxide film, and is injected to the floating gate 66.
On the other hand, the data (electron) is erased by grounding the control gate 65 and the selection gate 64, applying a voltage of about 12 V to the drain area 62, and extracting the electron to the drain area 62 from the floating gate 66 by F-N tunnel effect.
As described above, in EEPROM of FIG. 7, the program current is suppressed to be low by the selecting transistor 64 and the electron is injected along a traveling direction of the electron from the source side of the floating gate 66. Therefore, the EEPROM has a feature in which an electron injection efficiency is better than a usual hot electron injection in which electrons are injected from the drain side.
However, in the EEPROM of FIG. 7, the floating gate is formed of a conductive material such as poly-silicon. When the floating gate is formed of the conductive material, the floating gate causes capacity coupling with the control gate. Even if voltage is not directly applied to the floating gate, the voltage of the floating gate reaches an intermediate voltage between the voltage applied to the control gate and the ground voltage.
On the other hand, if the capacity coupling the floating gate and the control gate is small, the voltage of the floating gate is lowered; as a result, the electron injection efficiency deteriorates. Therefore, as shown in FIG. 8, it is necessary to enlarge the surface area of the floating gate as much as possible, so that a coupling ratio between the floating gate and the control gate becomes high. It is thus difficult to reduce the cell size, which obstructs high integration.